1. Field of the Invention
The invention relates to the field of semiconductor device fabrication techniques and devices and, more particularly, to the field of fabrication techniques for achieving very large scale integrated (VSLI) circuits and to the resulting device configurations of VSLI circuits.
2. Prior Art
The semiconductor art has been concerned with reducing the size and power consumption of individual devices in integrated circuits in order to increase the logic power of these circuits per unit area. Many things have been done over the years to reduce the size of devices and improve the tolerances with which they are fabricated. Such efforts have included, inter alia, fine line lithography, improved mask generation and alignment machines, improved tolerances on mask alignment, and self-aligned gates. These techniques have reduced the area required for fabrication of an individual device. However, because of alignment tolerances, devices must be designed with larger geometries than they would have to be if perfect mask alignment were attained.
Consequently, there is a need for improved mask alignment techniques for fabrication techniques having reduced sensitivity to mask alignment.